LTC1646
11
1646fa
Power-Down Sequence
When BD_SEL# is pulled high, a power-down sequence
begins (Figure 3).
Internal switches are connected to each of the output
supply voltage pins to discharge the bypass capacitors to
ground. The TIMER pin (Pin 2) is immediately pulled low.
The GATE pin (Pin 10) is pulled down by a 200礎 current
source to prevent the load currents on the 3.3V and 5V
supplies from going to zero instantaneously in order to
prevent glitching the power supply voltages. When either
of the output voltages dips below its threshold, HEALTHY#
pulls high and LOCAL_PCI_RST# will be asserted low.
Once the power-down sequence is complete, the CPCI
card may be removed from the slot. During extraction, the
precharge circuit will continue to bias the bus I/O pins at
1V until the 5V and 3.3V long connector pin connections
are separated.
Timer
During a power-up sequence, a 5礎 current source is
connected to the TIMER pin and current limit faults are
ignored until the voltage exceeds 1.25V. This feature
allows the chip to power up CPCI boards with widely
varying capacitive loads on the supplies. The power-up
time for either of the two outputs is given by:
t XV
C
XV
I
I
ON
OUT
LOAD XVOUT
OUT
LIMIT XVOUT LOAD XVOUT
(
)
"
"
(
)
(
)
(
)
= 2
(2)
Where XV
OUT
= 5V
OUT
or 3V
OUT
. For example, for
C
LOAD
(5V
OUT
) = 2000礔, I
LIMIT
= 7A, and I
LOAD
= 5A, the
5V
OUT
turn-on time will be ~10ms. By substituting the
variables in Equation 2 with the appropriate values, the
turn-on time for the 3V
OUT
output can also be calculated.
The timer period should be set longer than the maximum
supply turn-on time but short enough to not exceed the
maximum safe operating area of the pass transistor during
a short-circuit. The timer period for the LTC1646 is given
by:
t
C
V
A
TIMER
TIMER
=
?/DIV>
" .
1 25
5
(3)
As a design aid, the timer period as a function of the timing
capacitor using standard values from 0.01礔 to 1礔 is
shown in Table 2.
20ms/DIV
GATE
10V/DIV
5V
OUT
3V
OUT
5V/DIV
TIMER
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
LCL_PCI_RST#
5V/DIV
PRECHARGE
5V/DIV
1646 F02
GATE
10V/DIV
5V
OUT
3V
OUT
5V/DIV
TIMER
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
CL_PCI_RST#
5V/DIV
PRECHARGE
5V/DIV
1 4 F
Figure 2. Normal Power-Up Sequence
Figure 3. Normal Power-Down Sequence
APPLICATIO S I FOR ATIO
U
U
U
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